Semiconductor device having local interconnection layer and method for manufacturing the same

ABSTRACT

A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device and amethod for manufacturing the same, and more particularly, to asemiconductor device having a local interconnection layer and a methodfor manufacturing the same.

[0003] 2. Description of the Related Art

[0004] As the size of electronic products such as mobile phones, videotape recorders (VTRs), and notebooks becomes smaller, the size of thesemiconductor devices used in those electronic products also becomessmaller. As a result, in a process of manufacturing the semiconductordevices, the design rule used to control the size of the devices alsobecomes smaller.

[0005] In order to improve the electrical performance of a semiconductordevice, a shallow junction is used as a source/drain region.

[0006]FIG. 1 is a sectional view of a semiconductor device having aconventional local interconnection layer. Referring to FIG. 1, anisolation layer 10, for example, a trench isolation layer, is formed ina semiconductor substrate 20. Subsequently, a gate pattern 16 is formedby a conventional method on an active region of the semiconductorsubstrate 20, which is defined by the isolation layer 10. Next, impurityions are implanted into the semiconductor substrate 20, thereby forminga junction layer 12 on the semiconductor substrate 20 at both sides ofthe gate pattern 16. In general, the junction layer 12 is a shallowjunction layer. Subsequently, an interlayer dielectric (ILD) layer 22 isformed to be thick on the entire surface of the semiconductor substrate20 on which the junction layer 12 is formed and on the isolation layer10. Then, part of the ILD layer 22 is etched to form a contact hole.Finally, a local interconnection layer 14 is formed filling the contacthole.

[0007] However, according to a conventional method for manufacturing asemiconductor device, the isolation layer 10 is etched when forming thelocal interconnection layer 14. The isolation layer 10 is etched to bedeeper than the junction layer 12. In such a case, leakage currentoccurs in a direction A shown in FIG. 1, resulting in lowering theelectrical characteristics of the semiconductor device.

[0008] The reason the isolation layer 10 is etched to be deeper than thejunction layer 12 is as follows. First, the junction layer 12 becomesthinner while a semiconductor device is formed. The contact hole forforming the local interconnection layer 14 is formed by a dry etchprocess. However, it is very difficult to form the contact hole having adepth shallower than the junction layer 12 by finely adjusting the etchselectivity. Thus, the isolation layer 10 is etched to be deeper thanthe junction layer 12.

[0009] The electrical performance of a semiconductor device is loweredby the leakage current, and leakage current is a factor that lowers theyield of a process of manufacturing a semiconductor device.

SUMMARY OF THE INVENTION

[0010] To solve the above problems, it is a first objective of thepresent invention to provide a semiconductor device which is capable ofpreventing leakage current caused by etching an isolation layer,improving the electrical characteristics of a semiconductor device, andimproving the yield of a process of manufacturing a semiconductor device

[0011] It is a second objective of the present invention to provide amethod for manufacturing a semiconductor device which is capable ofpreventing leakage current caused by etching the isolation layer,improving the electrical characteristics of a semiconductor device, andimproving the yield of a process of manufacturing a semiconductordevice.

[0012] In accordance with the invention, there is provided asemiconductor device having a local interconnection layer. Thesemiconductor device includes an isolation layer, a junction layer, aninterlayer dielectric (ILD) layer, a local interconnection layer, and anetch stopper pattern. The isolation layer defines an active region of asemiconductor substrate at both sides of a gate pattern. The junctionlayer is formed on the semiconductor substrate at both sides of the gatepattern. The interlayer dielectric (ILD) layer covers the semiconductorsubstrate, the isolation layer, and the gate pattern. The localinterconnection layer is formed in the ILD layer on the isolation layerand the junction layer. The etch stopper pattern has at least one layerthat prevents the etching of the isolation layer under the localinterconnection layer.

[0013] In accordance with another aspect of the invention, there isprovided a method for manufacturing a semiconductor device having alocal interconnection layer. Impurity ions are implanted into asemiconductor substrate, on which an isolation layer and a gate patternare formed, and a junction layer is formed on the semiconductorsubstrate. An etch stopper having at least one layer on the isolationlayer and the junction layer is etched, and an etch stopper pattern forpreventing the etching of the isolation layer is formed. An interlayerdielectric (ILD) layer on the junction layer, the gate pattern, and theetch stopper are etched, and a contact hole on which a localinterconnection layer is to be formed is formed. The localinterconnection layer is formed by filling the contact hole with aconductive material.

[0014] In the semiconductor device having a local interconnection layeraccording to the present invention and the method for manufacturing thesame, leakage current caused by etching the isolation layer can beprevented, thereby improving the electrical characteristics of asemiconductor device and improving the yield of a process ofmanufacturing a semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The foregoing and other objects, features and advantages of theinvention will be apparent from the more particular description of apreferred embodiment of the invention, as illustrated in theaccompanying drawings in which like reference characters refer to thesame parts throughout the different views. The drawings are notnecessarily to scale, emphasis instead being placed upon illustratingthe principles of the invention.

[0016]FIG. 1 is a sectional view of a semiconductor device having aconventional local interconnection layer.

[0017]FIG. 2 is a plan view of a semiconductor device having a localinterconnection layer according to the present invention.

[0018]FIGS. 3 through 16 are sectional views illustrating asemiconductor device having a local interconnection layer according tofirst through fourth embodiments of the present invention and a methodfor manufacturing the same.

DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be described more fully hereinafterwith reference to the accompanying drawings in which preferredembodiments of the invention are shown. In the drawings, the forms ofelements are exaggerated for clarity. It will be understood that when alayer is referred to as being on another layer or on a semiconductorsubstrate, it can be directly on the other layer or on the semiconductorsubstrate, or intervening layers may also be present.

[0020]FIG. 2 is a plan view of a semiconductor device having a localinterconnection layer according to the present invention. Referring toFIG. 2, a gate pattern 104 is formed on an active region of asemiconductor substrate (100 of FIG. 3), which is defined by anisolation layer 102, for example, a trench isolation layer. Next,impurity ions are implanted into the semiconductor substrate 100,thereby forming a junction layer 110 on the semiconductor substrate 100at both sides of the gate pattern 104. In general, the junction layer110 is a shallow junction layer. A local interconnection region 112 isformed on the junction layer 110 and on the isolation layer 102. Here,I-I and II-II denote cut lines to be described later.

[0021]FIGS. 3 through 7 are sectional views illustrating a semiconductordevice having a local interconnection layer according to a firstembodiment of the present invention and a method for manufacturing thesame. Hereinafter, the local interconnection region 112 is referred toas a local interconnection layer 112. The local interconnection layer112 will be described with reference to FIG. 2 taken along line I-I, andthe gate pattern 104 will be described with reference to FIG. 2 takenalong line II-II.

[0022] Referring to FIG. 3, impurity ions are implanted into thesemiconductor substrate 100 on which the isolation layer 102 and thegate pattern 104 are formed, thereby forming the junction layer 110.Specifically, impurity ions for forming the junction layer 110 areimplanted into the semiconductor substrate 100 on which the isolationlayer 102 and the gate pattern 104 are formed, by using the gate pattern104 as an ion implantation mask. Impurity ions are implanted at a doseof 1-9×10¹⁴ atoms/cm² and with an energy of about 10 KeV. Afterperforming this process, the junction layer 110 is formed on thesemiconductor substrate 100 at both sides of the gate pattern 104.

[0023] A spacer 106 is formed on sidewalls of the gate pattern 104.Next, a source/drain region (not shown) having a deep junction layer isformed using the gate pattern 104 including the spacer 106 as animpurity ion implantation mask. As occasion demands, a thermal treatmentprocess can be performed after the junction layer 110 is formed or aftera source/drain region (not shown) is formed.

[0024] A first etch stopper 108 is formed on the isolation layer 102 andthe junction layer 110. Preferably, the first etch stopper 108 is formedof silicon nitride (Si₃N₄), and the thickness of silicon nitride (Si₃N₄)is 300-700 Å.

[0025] Referring to FIG. 4, a first photoresist pattern 112 for coveringthe isolation layer 102 and part of the junction layer 110 is formed onthe first etch stopper 108.

[0026] Referring to FIG. 5, the first etch stopper 108 is etched usingthe first photoresist pattern 112 as an etching mask, thereby forming afirst etch stopper pattern 108 a for exposing the junction layer 110.The etching time for etching the first etch stopper 108 can be adjustedso that the thickness of the first etch stopper 108 can be consideredwith respect to the etching rate of the etchant.

[0027] The isolation layer 102 and part of the junction layer 110 arecovered by the first etch stopper pattern 108 a. Specifically,preferably, the first etch stopper pattern 108 a of the junction layer110 is formed on a region that extends 0.05-0.3 μm from the end of theisolation layer 102 toward the junction layer 110. Even though part ofthe junction layer 110 is covered by the first etch stopper pattern 108a, the first etch stopper pattern 108 a prevents the etching of theisolation layer 102. The first etch stopper pattern 108 a can be formedby covering part of the junction layer 110. Subsequently, an interlayerdielectric (ILD) layer 114 is formed on the junction layer 110, the gatepattern 104, and the first etch stopper pattern 108 a.

[0028] Referring to FIG. 6, the ILD layer 114 is etched to form acontact hole 115 in which a local interconnection layer 116 is to beformed. When forming the local interconnection layer 116, part of thefirst etch stopper 108 a is not removed, instead, it is left to serve asan etch stopper to prevent the etching of the isolation layer 102. Thus,leakage current (A of FIG. 1) flowing from the local interconnectionlayer 116 to the semiconductor substrate 100 can be prevented.

[0029] The local interconnection layer 116 is formed of a conductivematerial filling the contact hole 115. Next, the conductive material onthe surface of the ILD layer 114 is removed by performing a chemicalmechanical polishing (CMP) process, leaving the local interconnectionlayer 116 formed in the contact hole 115.

[0030] According to the first embodiment, the first etch stopper pattern108 a may remain on the isolation layer 102 on which the localinterconnection layer 116 is not formed. As described above, even thoughthe first etch stopper pattern 108 a remains on the isolation layer 102,the first etch stopper pattern 108 a does not affect the characteristicsof a semiconductor device. Further, a remaining layer or pattern is notremoved, thereby reducing the time for the manufacturing process andmore stably forming a semiconductor device.

[0031]FIGS. 7 through 10 are sectional views illustrating asemiconductor device having a local interconnection layer according to asecond embodiment of the present invention and a method formanufacturing the same.

[0032] A second etch stopper 208 comprised of a first silicon nitride(Si₃N₄) layer 202, a silicon oxide (SiO₂) layer 204, and a secondsilicon nitride (Si₃N₄) layer 206 is formed on the isolation layer 102and the junction layer 110, which are formed according to the samemethod as that of FIG. 3. Preferably, the thickness of the first andsecond silicon nitride (Si₃N₄) layers 202 and 204 is 300-700 Å.

[0033] Referring to FIG. 8, a second photoresist pattern 210 forcovering the isolation layer 102 and part of the junction layer 110 isformed on the second etch stopper 208.

[0034] Referring to FIG. 9, the second silicon nitride (Si₃N₄) layer 206is etched using the second photoresist pattern 210 as an etching mask,thereby forming a second silicon nitride (Si₃N₄) layer pattern 206 a forexposing the silicon oxide (SiO₂) layer 204. The reason the secondsilicon nitride (Si₃N₄) layer 206 is selectively etched is that thesilicon oxide (SiO₂) layer 204 is used in forming a localinterconnection layer (116 of FIG. 10) in a subsequent process.

[0035] The isolation layer 102 and part of the junction layer 110 arecovered by the second silicon nitride (Si₃N₄) layer pattern 206 a.Specifically, preferably, the second silicon nitride (Si₃N₄) layerpattern 206 a over the junction layer 110 is formed on a region thatextends 0.05-0.3 μm from the end of the isolation layer 102 toward thejunction layer 110. Even though part of the junction layer 110 iscovered by the second silicon nitride (Si₃N₄) layer 206 a, the secondsilicon nitride (Si₃N₄) layer pattern 206 a prevents the etching of theisolation layer 102. The second silicon nitride (Si₃N₄) layer pattern206 a can be easily formed by covering part of the junction layer 110.Subsequently, an interlayer dielectric (ILD) layer 114 is formed on thesecond silicon nitride (Si₃N₄) layer pattern 206 a, the silicon oxide(SiO₂) layer 204, and the gate pattern 104.

[0036] Referring to FIG. 10, the ILD layer 114 is etched to form acontact hole 115 in which a local interconnection layer 116 is to beformed. The second silicon nitride (Si₃N₄) layer pattern 206 a, thesilicon oxide (SiO₂) layer 204, and the first silicon nitride (Si₃N₄)layer 202 are etched to form the contact hole 115. The etching rate isadjusted by the silicon oxide (SiO₂) layer 204 that is formed betweenthe second silicon nitride (Si₃N₄) layer pattern 206 a and the firstsilicon nitride (Si₃N₄) layer 202. Part of the first silicon nitride(Si₃N₄) layer 202 is not removed, instead, it is left to serve as anetch stopper to prevent the etching of the isolation layer 102. That is,a first silicon nitride (Si₃N₄) layer pattern 202 a for exposing thejunction layer 110 is formed using the second silicon nitride (Si₃N₄)layer pattern 206 a as an etching mask.

[0037] When forming the local interconnection layer 116, the firstsilicon nitride (Si₃N₄) layer pattern 202 a prevents the isolation layer102 from being etched. Thus, leakage current (A of FIG. 1) flowing fromthe local interconnection layer 116 to the semiconductor substrate 100can be prevented.

[0038] The local interconnection layer 116 is formed to fill the contacthole 115 with a conductive material. Next, the conductive material onthe surface of the ILD layer 114 is removed by performing a chemicalmechanical polishing (CMP) process, leaving the local interconnectionlayer 116 formed in the contact hole 115.

[0039] According to the second embodiment, the first silicon nitride(Si₃N₄) layer 202 and the silicon oxide (SiO₂) layer 204 may remain onthe junction layer 110 on which the local interconnection layer 116 isnot formed. The first silicon nitride (Si₃N₄) layer pattern 202 a, asilicon oxide (SiO₂) layer pattern 204 a, and the second silicon nitride(Si₃N₄) layer pattern 206 a may remain on the isolation layer 102 onwhich the local interconnection layer 116 is not formed. As describedabove, even though the first silicon nitride (Si₃N₄) layer pattern 202a, the silicon oxide (SiO₂) layer pattern 204 a, and the second siliconnitride (Si₃N₄) layer pattern 206 a remain on the isolation layer 102,the first silicon nitride (Si₃N₄) layer pattern 202 a, the silicon oxide(SiO₂) layer pattern 204 a, and the second silicon nitride (Si₃N₄) layerpattern 206 a do not affect the characteristics of a semiconductordevice. Further, a remaining layer or pattern is not removed, therebyreducing the time for the manufacturing process and more stably forminga semiconductor device.

[0040]FIGS. 11 through 13 are sectional views illustrating asemiconductor device having a local interconnection layer according to athird embodiment of the present invention and a method for manufacturingthe same.

[0041] Referring to FIG. 11, a third photoresist pattern 212 forcovering part of the isolation layer 102 is formed on the first etchstopper 108, which is formed according to the same method as that ofFIG. 3.

[0042] Referring to FIG. 12, the first etch stopper 108 is etched usingthe third photoresist pattern 212 as an etching mask, thereby forming afirst etch stopper pattern 108 a for exposing the junction layer 110.The etching time for etching the first etch stopper 108 can be adjustedso that the thickness of the first etch stopper 108 can be consideredwith respect to the etching rate of an etchant.

[0043] Part of the isolation layer 102 is exposed by the first etchstopper pattern 108 a. Specifically, preferably, the first etch stopperpattern 108 a is formed on a region that extends 0.05-0.3 μm from theend of the junction layer 110 to the inside of the isolation layer 102.This is how etching of the isolation layer 102 can be prevented and thefirst etch stopper pattern 108 a can be readily formed even though partof the isolation layer 102 is exposed by the first etch stopper pattern108 a. Subsequently, an interlayer dielectric (ILD) layer 114 is formedon the junction layer 110, the gate pattern 104, and the first etchstopper pattern 108 a.

[0044] Referring to FIG. 13, the ILD layer 114 is etched to form acontact hole 115 in which a local interconnection layer 116 is to beformed. When forming the local interconnection layer 116, the first etchstopper pattern 108 a prevents the isolation layer 102 from beingetched. Thus, leakage current (A of FIG. 1) flowing from the localinterconnection layer 116 to the semiconductor substrate 100 can beprevented.

[0045] The local interconnection layer 116 is formed of a conductivematerial filling the contact hole 115. Next, the conductive material onthe surface of the ILD layer 114 is removed by performing a chemicalmechanical polishing (CMP) process, leaving the local interconnectionlayer 116 formed in the contact hole 115.

[0046] According to the third embodiment, the first etch stopper pattern108 a may remain on the isolation layer 102 on which the localinterconnection layer 116 is not formed. As described above, even thoughthe first etch stopper pattern 108 a remains on the isolation layer 102,the first etch stopper pattern 108 a does not affect the characteristicsof a semiconductor device. Further, a remaining layer or pattern is notremoved, thereby reducing the time for the manufacturing process andmore stably forming a semiconductor device.

[0047]FIGS. 14 through 16 are process sectional views illustrating asemiconductor device having a local interconnection layer according to afourth embodiment of the present invention and a method formanufacturing the same.

[0048] Referring to FIG. 14, a fourth photoresist pattern 214 forcovering part of the isolation layer 102 is formed on the second etchstopper 208 according to the same method as that of FIG. 7.

[0049] Referring to FIG. 15, the second silicon nitride (Si₃N₄) layer206 is etched using the fourth photoresist pattern 214 as an etchingmask, thereby forming a second silicon nitride (Si₃N₄) layer pattern 206a for exposing the silicon oxide (SiO₂) layer 204. The reason the secondsilicon nitride (Si₃N₄) layer 206 is selectively etched is that thesilicon oxide (SiO₂) layer 204 is used in forming a localinterconnection layer (116 of FIG. 16) in a subsequent process.

[0050] The isolation layer 102 is exposed by the second silicon nitride(Si₃N₄) layer pattern 206 a. Specifically, preferably, the secondsilicon nitride (Si₃N₄) layer pattern 206 a is formed on a region thatextends 0.05-0.3 μm from the end of the junction layer 110 to the insideof the isolation layer 102. Even though upper part of the isolationlayer 102 is exposed by the second silicon nitride (Si₃N₄) layer 206 a,the second silicon nitride (Si₃N₄) layer pattern 206 a prevents theetching of the isolation layer 102. The second silicon nitride (Si₃N₄)layer pattern 206 a can be easily formed by exposing upper part of theisolation layer 102. Subsequently, an interlayer dielectric (ILD) layer114 is formed on the second silicon nitride (Si₃N₄) layer pattern 206 a,the silicon oxide (SiO₂) layer 204, and the gate pattern 104.

[0051] Referring to FIG. 16, the ILD layer 114 is etched to form acontact hole 115 in which a local interconnection layer 116 is to beformed. The second silicon nitride (Si₃N₄) layer pattern 206 a, thesilicon oxide (SiO₂) layer 204, and the first silicon nitride (Si₃N₄)layer 202 are etched to form the contact hole 15. The second siliconnitride (Si₃N₄) layer pattern 206 a and the silicon oxide (SiO₂) layer204 in the contact hole 115 are etched by the etching process. Thesilicon oxide (SiO₂) layer 204 adjusts an etching rate between thesecond silicon nitride (Si₃N₄) layer pattern 206 a and the first siliconnitride (Si₃N₄) layer 202. Part of the first silicon nitride (Si₃N₄)layer 202 is not removed, instead, it is left to serve as an etchstopper to prevent the etching of the isolation layer 102. That is, afirst silicon nitride (Si₃N₄) layer pattern 202 a for exposing thejunction layer 110 is formed using the second silicon nitride (Si₃N₄)layer pattern 206 a as an etching mask.

[0052] When forming the local interconnection layer 116, the firstsilicon nitride (Si₃N₄) layer pattern 202 a prevents the isolation layer102 from being etched. Thus, leakage current (A of FIG. 1) flowing fromthe local interconnection layer 116 to the semiconductor substrate 100can be prevented.

[0053] The local interconnection layer 116 is formed of a conductivematerial filling the contact hole 115. Next, the conductive material onthe surface of the ILD layer 114 is removed by performing a chemicalmechanical polishing (CMP) process. As a result, the localinterconnection layer 116 is formed on the contact hole 115.

[0054] According to the fourth embodiment, the first silicon nitride(Si₃N₄) layer 202 and the silicon oxide (SiO₂) layer 204 may remain onthe junction layer 110 on which the local interconnection layer 116 isnot formed. The first silicon nitride (Si₃N₄) layer pattern 202 a, asilicon oxide (SiO₂) layer pattern 204 a, and the second silicon nitride(Si₃N₄) layer pattern 206 a may remain on the isolation layer 102 onwhich the local interconnection layer 116 is not formed. As describedabove, even though the first silicon nitride (Si₃N₄) layer pattern 202a, the silicon oxide (SiO₂) layer pattern 204 a, and the second siliconnitride (Si₃N₄) layer pattern 206 a remain on the isolation layer 102,the first silicon nitride (Si₃N₄) layer pattern 202 a, the silicon oxide(SiO₂) layer pattern 204 a, and the second silicon nitride (Si₃N₄) layerpattern 206 a do not affect the characteristics of a semiconductordevice. Further, a remaining layer or pattern is not removed, therebyreducing the time for the manufacturing process and more stably forminga semiconductor device.

[0055] As described above, in the semiconductor device having a localinterconnection layer according to the present invention and the methodfor manufacturing the same, the etch stopper pattern having at leastmore than one layer for preventing the etching of the isolation layercan be included when forming the local interconnection layer, therebypreventing leakage current caused by the etching of the isolation layer,improving the electrical characteristics of a semiconductor device, andimproving the yield of a process of manufacturing a semiconductordevice.

[0056] While this invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein without departing from the spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. A semiconductor device having a localinterconnection layer, the semiconductor device comprising: an isolationlayer for defining an active region of a semiconductor substrate at bothsides of a gate pattern; a junction layer formed on the semiconductorsubstrate at both sides of the gate pattern; an interlayer dielectric(ILD) layer for covering the semiconductor substrate, the isolationlayer, and the gate pattern; a local interconnection layer formed in theILD layer on the isolation layer and the junction layer; and an etchstopper pattern having at least one layer for preventing the etching ofthe isolation layer under the local interconnection layer.
 2. Thesemiconductor device of claim 1, wherein the isolation layer and part ofthe junction layer are covered by the etch stopper pattern.
 3. Thesemiconductor device of claim 2, wherein the etch stopper pattern isformed on a region that extends 0.05-0.3 μm from the end of the junctionlayer to the inside of the isolation layer.
 4. The semiconductor deviceof claim 1, further comprising an etch stopper having at least onelayer, for covering part of the isolation layer.
 5. The semiconductordevice of claim 4, wherein the etch stopper pattern does not cover aregion that extends 0.05-0.3 μm from the end of the junction layer tothe inside of the isolation layer.
 6. The semiconductor device of claim1, wherein the etch stopper pattern includes a silicon nitride (Si₃N₄)layer.
 7. The semiconductor device of claim 6, wherein the thickness ofthe silicon nitride (Si₃N₄) layer is 300-700 Å.
 8. The semiconductordevice of claim 1, wherein the etch stopper pattern remains on theisolation layer on which the local interconnection layer is not formed.9. The semiconductor device of claim 1, wherein the etch stopper patternis comprised of a first silicon nitride (Si₃N₄) layer, a silicon oxide(SiO₂) layer, and a second silicon nitride (Si₃N₄) layer.
 10. Thesemiconductor device of claim 9, wherein the first silicon nitride(Si₃N₄) layer and the silicon oxide (SiO₂) layer remain on the junctionlayer on which the local interconnection layer is not formed.
 11. Thesemiconductor device of claim 9, wherein the first silicon nitride(Si₃N₄) layer, the silicon oxide (SiO₂) layer, and the second siliconnitride (Si₃N₄) layer remain on the isolation layer on which the localinterconnection layer is not formed.
 12. A method for manufacturing asemiconductor device having a local interconnection layer, the methodcomprising: implanting impurity ions into a semiconductor substrate, onwhich an isolation layer and a gate pattern are formed, and forming ajunction layer on the semiconductor substrate; etching an etch stopperhaving at least one layer on the isolation layer and the junction layerand forming an etch stopper pattern for preventing the etching of theisolation layer; etching an interlayer dielectric (ILD) layer on thejunction layer, the gate pattern, and the etch stopper, and forming acontact hole on which a local interconnection layer is to be formed; andforming the local interconnection layer by filling the contact hole witha conductive material.
 13. The method of claim 12, wherein the etchstopper pattern covers the isolation layer and part of the junctionlayer.
 14. The method of claim 12, wherein the etch stopper patterncovers part of the isolation layer.
 15. The method of claim 12, whereinthe etch stopper pattern includes a silicon nitride (Si₃N₄) layer. 16.The method of claim 15, wherein the thickness of the silicon nitride(Si₃N₄) layer is 300-700 Å.
 17. The method of claim 12, wherein the etchstopper pattern remains on the isolation layer on which the localinterconnection layer is not formed.
 18. The method of claim 12, whereinthe etch stopper pattern is comprised of a first silicon nitride (Si₃N₄)layer, a silicon oxide (SiO₂) layer, and a second silicon nitride(Si₃N₄) layer.
 19. The method of claim 18, wherein the first siliconnitride (Si₃N₄) layer and the silicon oxide (SiO₂) layer remain on thejunction layer on which the local interconnection layer is not formed.20. The method of claim 18, wherein the first silicon nitride (Si₃N₄)layer, the silicon oxide (SiO₂) layer, and the second silicon nitride(Si₃N₄) layer remain on the isolation layer on which the localinterconnection layer is not formed.